Non-volatile memory devices are used in applications requiring the storing of information that has to be retained even when the memory devices are not powered. Generally, each memory device includes a matrix of memory cells based on floating gate MOS storage transistors; each storage transistor has a threshold voltage that may be set (according to an electric charge in its floating gate) to different levels representing corresponding logic values.
For example, in Electrical Erasable and Programmable Read-Only Memories (E2PROMs) each storage transistor may be both programmed (by injecting electric charge into its floating gate) and erased (by removing electric charge from its floating gate) individually—thanks to the use of a set of MOS selection transistors that apply the required voltages selectively to the corresponding storage transistor (with a quite complex structure that limits the capacity of the E2PROMs to a few Kbytes). On the other hand, flash memories have a simple structure that allows obtaining very high capacities thereof, up to some Gbytes—thanks to the grouping of the memory cells in sectors each one integrated in a common well of semiconductor material without any selection transistor (with the need of erasing the flash memories at the sector level).
In both cases, a production process of the memory devices substantially differs from a standard one (for example, in CMOS-technology). Indeed, the storage transistors may require an additional polysilicon layer to define their floating gates (besides the one used to define their control gates as in the CMOSs). This difference may add design complexity, which may significantly increase the manufacturing cost of the memory devices (of the order of 30% with respect to standard CMOS devices).
In order to solve these problems, Few Time Programmable (FTP) or Cost-Effective memories have been proposed in the last years. In the FTP memories, the memory cells are again grouped in sectors (integrated in corresponding wells). However, the storage transistor of each memory cell now has a distinct control gate region being capacitively coupled with its floating gate; therefore, the FTP memories use a single polysilicon layer, so that they may be manufactured with the standard CMOS production process.
The FTP memories known in the art are generally based on a so-called emitter structure. Particularly, in the emitter-FTP memories, each memory cell includes, in addition to the storage transistor, an MOS selection transistor (being used to select the memory cell for its reading), and a stray BJT injection transistor (being used to implement its programming). The memory cells are programmed by hot electron injection (very fast through their injection transistors) and they are erased by Fowler-Nordheim effect. An example of emitter-FTP memory is described in U.S. Pat. No. 6,876,033 (the entire disclosure of which is herein incorporated by reference).
This makes the FTP memories very attractive for the embedding of memories of small capacity (up to some Kbytes) into CMOS devices; indeed, in this case it may possible to add the FTP memories at low cost and very quickly (since they do not require complex re-design and test operations).
However, FTP-memories may also have to be erased at the sector level. Moreover, they may require very high voltages (both positive and negative) for programming and erasing the memory cells, and high currents for their programming. Particularly, in the emitter-FTP memories the injection transistors have a stray structure; therefore, the injection transistors may not be characterized accurately, and thus they may have be over-dimensioned to ensure the required performance in every anticipating operating condition. Therefore, the currents that are used during the programming of the memory cells may further increase (up to 0.1-5 mA). This may require very complex charge pumps to generate the required high voltages (from a lower power supply voltage), and at the same time provide the required high currents. In addition, the high voltages and currents may involve large power consumption. These high currents may also limit a programming parallelism (for example, to 8 memory cells). Moreover, during the erasing of a selected sector, the high voltages applied to its memory cells may in part propagate to the other memory cells that are capacitively coupled thereto. As a result, these memory cells may be subject to an electric stress that causes a loss of electric charge in the floating gates of their storage transistors, with an undesired erasing of the memory cells after repeated erasing operations on nearby cells. This may limit a data retention of the memory cells, and then a number of erasing operations that may be withstood (of the order of a few thousands).